1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a bipolar complementary metal-oxide semiconductor device (hereinafter referred to as a xe2x80x9cBi-CMOS devicexe2x80x9d) and a method of manufacturing the same.
2. Description of the Background Art
FIG. 23 is a cross-sectional structural view of a conventional Bi-CMOS device. As shown in the figure, the conventional Bi-CMOS device is constructed so that an NPN bipolar transistor, a P-channel MOS transistor, and an N-channel MOS transistor are formed on a P-type semiconductor substrate 1.
The NPN bipolar transistor includes a heavily doped N-type buried layer 2 formed in the lightly doped P-type semiconductor substrate 1, a lightly doped N-type collector layer 3, a heavily doped N-type contact collector layer 4, a P-type isolating layer 7, a heavily doped P-type outer base layer 8, a moderately doped P-type base layer 9, a heavily doped N-type emitter layer 10, a base electrode 200, and an emitter electrode 301. The NPN bipolar transistor further includes an element isolating oxide film 101, an oxide film 104, a thermal oxide film 105, a sidewall oxide film 106, and an oxide film 107. The emitter electrode 301 is formed with a polycrystalline silicon film in which arsenic is generally introduced as an N-type impurity.
The P-channel MOS transistor includes a lightly doped N-type well layer 5 formed in the P-type semiconductor substrate 1, a heavily doped P-type source/drain layer 11, a gate oxide film 102, an oxide film 107, and a gate electrode 401. Here, the gate electrode 401 is formed with upper and lower polycrystalline silicon films 502 and 501 in which arsenic is generally introduced as an N-type impurity. The upper polycrystalline silicon film 502 is the same film as the emitter electrode 301 of the NPN bipolar transistor.
The N-channel MOS transistor includes a lightly doped P-type well layer 6 formed in the P-type semiconductor 1, a heavily doped N-type source/drain layer 12, a gate oxide film 102, an oxide film 107, and a gate electrode 402. Here, the gate electrode 402 is formed with the same upper and lower polycrystalline silicon films 502 and 501 as the gate electrode 401 of the P-channel MOS transistor.
The NPN bipolar, P-channel MOS, and N-channel MOS transistors are isolated from one another by the element isolating oxide films 101, and each transistor surface is covered with an oxide film 108, in which contact holes 601, 602, 603, 606, and 607 and a metal wire 700 are formed.
Next, FIG. 24 is a cross-sectional structural view showing one step of the method of manufacturing the conventional Bi-CMOS device. The method of manufacturing the conventional Bi-CMOS device will be described with reference to FIGS. 23 and 24.
In the conventional manufacturing method, a heavily doped N-type buried layer 2 is first formed in the NPN bipolar transistor formation region of the lightly doped P-type semiconductor substrate 1, and then a lightly doped N-type epitaxial layer 3 is grown on the entire surface. Thereafter, the element isolating oxide film 101 is formed on each element isolating region and across the collector and base layer of the bipolar transistor. Subsequently, the heavily doped N-type collector layer 4 of the NPN bipolar transistor is formed on a collector contact portion, and the lightly doped N-type well layer S of the P-channel MOS transistor, and the lightly doped P-type well layer 6 of the N-channel MOS transistor are formed, respectively. Furthermore, a moderately doped P-type isolating layer 7 is formed in the N-type epitaxial layer 3 and between the N-type epitaxial layer 3 and the N-type well layer 5. Note that the N-type epitaxial layer 3 becomes the N-type collector layer 3 of the NPN bipolar transistor.
Next, a gate oxide film 102 is formed on each surface of the N-type collector layer 3, the N-type collector contact layer 4, the N-type well layer 5, and the P-type well layer 6. Further, a lower polycrystalline silicon film 501 is formed on the entire surface of the gate oxide film 102.
Next, the lower polycrystalline silicon film 501 and the gate oxide film 102 on the surface of the N-type collector 3 are removed, and a polycrystalline silicon film 500 is formed on the entire surface. Then, boron ions are implanted into the polycrystalline silicon film 500 so that it becomes a P-type.
Next, an oxide film 104 is formed on the entire surface of the polycrystalline silicon film 500. The oxide film 104 and the polycrystalline silicon film 500 are removed in sequence, while the films 104 and 500, deposited on the outer base layer formation region of the NPN bipolar transistor and on a portion of the element isolating oxide film 101, are not removed. Next, a thermal oxide film 105 is formed on the surface of the N-type collector 3 from which the polycrystalline silicon film 500 has been removed, and at the same time, a heavily doped P-type outer base layer 8 is formed by thermal diffusion of boron from the polycrystalline silicon film 500 into the N-type collector layer 3. Here, the polycrystalline silicon film 500 becomes the base electrode 200 of the NPN bipolar transistor. Further, boron ions are implanted through the thermal oxide film 105 to form a moderately doped P-type base layer 9 on the upper portion of the N-type collector layer 3.
Next, an oxide film is deposited on the entire surface, and side-wall oxide films 106 are formed on side surfaces of the base electrode 200 and the oxide film 104 by etching back the deposited oxide film. At this time, the thermal oxide film 105 is removed by over-etching.
Next, an upper polycrystalline silicon film 502 is formed on the entire surface, as shown in FIG. 24, and arsenic ions are implanted into the upper polycrystalline silicon film 502 and then annealing is performed. Then, arsenic is diffused from the upper polycrystalline silicon film 502 into the upper portion of the P-type base layer 9 to form a heavily doped N-type emitter 10. Simultaneously, arsenic is diffused into the lower polycrystalline silicon film 501 so that it becomes a N-type.
Furthermore, an oxide film 107 is deposited over the entire surface of the upper polycrystalline silicon film 502. As shown in FIG. 23, the oxide film 107, the upper polycrystalline silicon film 502, and the lower polycrystalline silicon film 501 are sequentially removed, while those on the emitter electrode formation region of the NPN bipolar transistor and the gate electrode formation regions of the MOS transistors are not removed. In this way, the emitter electrode 301, consisting of the upper polycrystalline silicon film 502, and the gate electrodes 401 and 402, consisting of the upper and lower polycrystalline silicon films 502 and 501, are formed. During these processes, the gate oxide film 102 serves as a protective film for each surface of the N-type collector contact layer 4, the N-type well layer 5, and the P-type well layer 6.
Next, the NPN bipolar transistor and the N-channel MOS transistor are covered with a photoresist film (not shown), and boron ions are implanted through the gate oxide film 102 to form a heavily doped P-type source/drain layer 11 on the upper portion of the N-type well layer 5, as shown in FIG. 23. When the ion implantation is performed, the oxide film 107 serves as a mask for the gate electrode 401. Next, the NPN bipolar transistor and the P-channel MOS transistor are covered with a photoresist film (not shown), and arsenic ions are implanted through the gate oxide film 102 to form a heavily doped N-type source/drain layer 12 on the upper portion of the P-type well layer 6. When the ion implantation is performed, the oxide film 107 serves as a mask for the gate electrode 402. Further, the P-type source/drain layer 11 and the N-type source/drain layer 12 are annealed and activated.
Thereafter, an oxide film 108 is deposited on the entire surface, and contact holes 601 through 609 are formed on the N-type collector contact layer 4, the base electrode 200, the emitter electrode 301, the N-type well layer 5, the P-type well layer 6, the P-type source/drain layer 11, the N-type source/drain layer 12, the gate electrode 401 of the P-channel MOS transistor, and the gate electrode 402 of the N-channel MOS transistor, respectively. An appropriate metal lead 700 is formed, and a device structure such as shown in FIG. 23, is obtained. Note that the contact holes 604, 605, 608, and 609 on the N-type well layer 5, the P-type well layer 6, and the gate electrodes 401 and 402 are formed on the regions not appearing in FIG. 23.
The foregoing is the structure of the conventional Bi-CMOS device and the method of manufacturing the same. Next, problems with the conventional Bi-CMOS device will be described.
First, the problems with the structure of the conventional Bi-CMOS device will be described.
FIG. 25 is a diagram showing the concentration distribution of arsenic along the A-Axe2x80x2 line of FIG. 23. The gate electrodes 401 and 402 of the N-channel and P-channel MOS transistors are each formed by the upper and lower polycrystalline silicon films 502 and 501 which contain arsenic. In the case where a polycrystalline silicon film containing arsenic is used in a gate electrode, there will be the possibility that arsenic will aggregate, as shown in FIG. 25, near the interface between the polycrystalline silicon film and the oxide film, thereby reducing the life of the gate oxide film.
For the aforementioned problem, an attempt has been made to suppress aggregation of arsenic by introducing nitrogen into the polycrystalline silicon film of the gate electrode and aggregating nitrogen near the interface between the polycrystalline silicon film and the gate oxide film. However, in this method the upper polycrystalline silicon films 502 of the gate electrodes 401 and 402 are the same film as the emitter electrode 301 of the NPN bipolar transistor. Therefore, if nitrogen is introduced into the gate electrodes 401 and 402, it will also be introduced into the emitter electrode 301. The nitrogen introduced into the emitter electrode 301 will give rise to a new problem in that it will aggregate near the interface between the emitter electrode 301 and the N-type emitter layer 10 and reduce the current amplification factor of the NPN bipolar transistor.
In addition, in the conventional Bi-CMOS device, the emitter electrode 301 and the gate electrodes 401 and 402 are formed with a polycrystalline silicon film, so the electrical resistance of each electrode is high and the loss of the consumption power is large.
Next, the problems with the method of manufacturing the conventional Bi-CMOS device will be described.
A first problem is as follows. In the process shown in FIG. 24, when arsenic ions are implanted into the upper polycrystalline silicon film 502, the implantation energy is normally set so that the arsenic ions do not reach the gate oxide film 102. However, the crystal grains of the upper and lower polycrystalline silicon films 502 and 501 have an arbitrary crystal orientation. Therefore, where the crystal orientation matches the implantation direction of arsenic ions, there are some cases where the arsenic ions reach the gate oxide film 102 or the well layer due to the channeling phenomenon where arsenic ions go down to a deeper position without colliding with crystal atoms. Thus, the problem is that the arsenic ions will cause damage to the atomic coupling of the gate oxide film 102 and induce a deterioration in the film quality.
A secondary problem will be described next. Generally, in the thermal diffusion of the impurities in the polycrystalline silicon film, high-speed diffusion takes place along the grain boundary. In the process shown in FIG. 24, arsenic ions are introduced into the upper polycrystalline silicon film 502, and then diffused from the upper polycrystalline silicon film 502 into the lower polycrystalline silicon film 501 to turn it to an N-type. Afterwards, the film 502 is annealed. Here, a possible problem exists that arsenic will reach the interface between the lower polycrystalline silicon film 501 and the gate oxide film 102, due to the high-speed diffusion along the grain boundary, and then aggregate near the interface. Thus the life of the gate oxide film will be reduced. Note that the aforementioned first and secondary problems also arise in the case where an N-type dopant other than arsenic, such as phosphorus, is used.
The present invention has been made in order to solve the aforementioned problems found in the conventional Bi-CMOS device.
The object of the present invention is to provide a semiconductor device, having a bipolar transistor and a MOS transistor on the same semiconductor substrate, and a manufacturing method thereof, which can prevent a deterioration in the film quality of a gate oxide film and prevent a reduction in the life of the gate oxide film.
According to one aspect of the present invention, a semiconductor device comprises at least one bipolar transistor and at least one metal-oxide semiconductor (MOS) transistor on a semiconductor substrate. The MOS transistor includes a gate oxide film and a gate electrode, and the gate electrode is comprised of a first electrode layer and a second electrode layer formed on said first electrode layer. The first electrode layer is in contact with said gate oxide film, and contains nitrogen aggregated around an interface with said gate oxide film. Further, the bipolar transistor includes an emitter electrode not containing nitrogen, and has a same film thickness as said second gate electrode layer of said MOS transistor.
In another aspect of the present invention, in the semiconductor device, a high-melting-point metal film or a silicide film of a high-melting-point metal is formed on said gate electrode of said MOS transistor and on said emitter electrode of said bipolar transistor, respectively.
In another aspect of the present invention, in the semiconductor device, said bipolar transistor is an NPN type, having an N-type emitter electrode, and a plurality of said MOS transistors that are a combination of complementary metal-oxide semiconductor (CMOS) transistors composed of a P-channel MOS type, having an N-type gate electrode, and an N-channel MOS type, having an N-type gate electrode.
In another aspect of the present invention, in the semiconductor device, said bipolar transistor is an NPN type having an N-type emitter electrode, and a plurality of said MOS transistors that are a combination of complementary metal-oxide semiconductor (CMOS) transistors composed of a P-channel MOS type, having a P-type gate electrode, and an N-channel MOS type having an N-type gate electrode.
In another aspect of the present invention, in the semiconductor device, a plurality of said bipolar transistors are a combination of an NPN type having an N-type emitter electrode and an PNP type having a P-type emitter electrode.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor on a semiconductor substrate, a gate oxide film is formed on a region of said semiconductor substrate for making a MOS transistor. A polycrystalline silicon film is formed and nitrogen is introduced into said polycrystalline silicon film to make a first gate electrode layer on said gate oxide film. An amorphous silicon film is formed on said polycrystalline silicon film to make a second gate electrode layer of said MOS transistor, and concurrently the amorphous silicon film is formed to make an emitter electrode on an emitter layer formation region of said semiconductor substrate for making a bipolar transistor. Then, impurities are implanted into said amorphous silicon film. Further, the nitrogen is aggregated around the interface between said polycrystalline silicon film and said gate oxide film by thermal treatment.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor on a semiconductor substrate, a gate oxide film is formed on a region of said semiconductor substrate for making a MOS transistor. A polycrystalline silicon film containing nitrogen is formed to make a first gate electrode layer on said gate oxide film for making a MOS transistor. An amorphous silicon film is formed on said polycrystalline silicon film to make a second gate electrode layer of said MOS transistor, and concurrently the amorphous silicon film is formed to make an emitter electrode on an emitter layer formation region of said semiconductor substrate. Then, impurities are implanted into said amorphous silicon film. Further, said nitrogen is aggregated around the interface between said polycrystalline silicon film and said gate oxide film by thermal treatment.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor on a semiconductor substrate, a gate oxide film is formed on a region of said semiconductor substrate for making a MOS transistor. A first polycrystalline silicon film is formed to make a first gate electrode layer on said gate oxide film. A second polycrystalline silicon film is formed on said first polycrystalline silicon film to make a second gate electrode layer of said MOS transistor, and concurrently the second polycrystalline silicon film is formed to make an emitter electrode on an emitter layer formation region of said semiconductor substrate for making a bipolar transistor. Then, nitrogen is implanted into said second polycrystalline silicon film, thereby an amorphous layer is formed in said second polycrystalline silicon film. Then, impurities are implanted into said second polycrystalline silicon film to a depth shallower than said amorphous layer. Further, said impurities and nitrogen are diffused from said second polycrystalline silicon film into said first polycrystalline silicon film, and said nitrogen is aggregated around the interface between said first polycrystalline silicon film and said gate oxide film by thermal treatment.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor on a semiconductor substrate, a gate oxide film is formed on a region of said semiconductor substrate for making a MOS transistor. A polycrystalline silicon film is formed to make a first gate electrode layer on said gate oxide film. An amorphous silicon film is formed on said polycrystalline silicon film to make a second gate electrode layer of said MOS transistor, and concurrently the amorphous silicon film is formed to make an emitter electrode on an emitter layer formation region of said semiconductor substrate for making a bipolar transistor. Then, nitrogen is implanted into said amorphous silicon film and then impurities are implanted into said amorphous silicon film. Further, said impurities and nitrogen are diffused from said amorphous silicon film into said polycrystalline silicon film, and said nitrogen is aggregated around the interface between said polycrystalline silicon film and said gate oxide film by thermal treatment.
According to another aspect of the present invention, a semiconductor device comprises at least one bipolar transistor and at least one metal-oxide semiconductor (MOS) transistor on a semiconductor substrate. The MOS transistor includes a gate electrode formed of a monocrystalline silicon film. The bipolar transistor includes an emitter electrode formed of a monocrystalline silicon film thinner than said monocrystalline silicon film of said gate electrode of said MOS transistor.
In another aspect of the present invention, in the semiconductor device, a high-melting-point metal film or a silicide film of a high-melting-point metal is formed on said gate electrode of said MOS transistor and on said emitter electrode of said bipolar transistor, respectively.
In another aspect of the present invention, in the semiconductor device, said bipolar transistor is an NPN type having an N-type emitter electrode, and a plurality of said MOS transistors that are a combination of complementary metal-oxide semiconductor (CMOS) transistors composed of a P-channel MOS type having an N-type gate electrode and an N-channel MOS type having an N-type gate electrode.
In another aspect of the present invention, in the semiconductor device, said bipolar transistor is an NPN type having an N-type emitter electrode, and a plurality of said MOS transistors that are a combination of complementary metal-oxide semiconductor (CMOS) transistors composed of a P-channel MOS type having a P-type gate electrode and an N-channel MOS type having an N-type gate electrode.
In another aspect of the present invention, in the semiconductor device, a plurality of said bipolar transistors are a combination of an NPN type having an N-type emitter electrode and an PNP type having a P-type emitter electrode.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor on a semiconductor substrate, a gate oxide film is formed on a region of said semiconductor substrate for making a MOS transistor. A first amorphous silicon film is formed to make a first gate electrode layer on said gate oxide film for making a MOS transistor, and said first amorphous silicon film is crystallized by thermal treatment to transform it into a first monocrystalline silicon film. A second amorphous silicon film is formed on said first monocrystalline silicon film to make a second gate electrode layer of said MOS transistor, and concurrently the second amorphous silicon film is formed to make an emitter electrode on an emitter layer formation region of said semiconductor substrate for making a bipolar transistor. Then, impurities are implanted into said second amorphous silicon film. Further, said impurities are diffused from said second amorphous silicon film into said first monocrystalline silicon film, and said second amorphous silicon film is crystallized to transform it into a second monocrystalline silicon film by thermal treatment.